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Pull requests: llvm/circt

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Pull requests list

[FIRRTL] Replace remove-unused-ports with port-only IMDCE mode
#10575 opened Jun 2, 2026 by uenoku Member Loading…
1
1
[Synth] Run structural hash on nested blocks
#10570 opened Jun 1, 2026 by uenoku Member Loading…
1
[HW] Change specification of union operations, NFC HW Involving the `hw` dialect
#10567 opened May 31, 2026 by fzi-hielscher Contributor Loading…
1
[LLHD] Fix incorrect mux generation in remove-control-flow
#10566 opened May 31, 2026 by vasyavasilevs Loading…
[Synth] Add declarative cut rewrite pattern and yield op
#10565 opened May 31, 2026 by okekayode Contributor Loading…
15
Add CIRCT standalone example
#10564 opened May 30, 2026 by uenoku Member Loading…
1
[ExportVerilog] Add a lowering option for always emitting begin/end
#10563 opened May 29, 2026 by uenoku Member Loading…
1
[RTG] Randomizer operations are not pure RTG Involving the `rtg` dialect
#10560 opened May 29, 2026 by maerhart Member Loading…
5
[Moore][ImportVerilog] Replace $sformat/$swrite string dispatch with ksn
#10557 opened May 28, 2026 by VecoMr Contributor Loading…
1
[Moore][Sim][SV] Add $strobe[boh] lowering via sim.defer
#10556 opened May 28, 2026 by VecoMr Contributor • Draft
2
[OM] Simplify evaluator placeholder handling, NFCI
#10555 opened May 28, 2026 by uenoku Member Loading…
1
[RFC][Sim] Add declarations and reads for externally controlled configuration bits
#10552 opened May 27, 2026 by nanjo712 Contributor Loading…
8
[Arc] Lower hw.triggered in Arc
#10550 opened May 27, 2026 by nanjo712 Contributor Loading…
1
[ImportVerilog] Add support for countones.
#10549 opened May 27, 2026 by jpienaar Member Loading…
6
[FIRRTLToHW] Add support for lower-to-core in firrtl.fflush
#10545 opened May 26, 2026 by nanjo712 Contributor Loading…
14
[LTL] Add ClockedAtomOp description
#10541 opened May 24, 2026 by Clo91eaf Contributor Loading…
5
[FIRRTLToHW] Remove the SYNTHESIS guard in printf/flush lowering path
#10526 opened May 22, 2026 by nanjo712 Contributor Loading…
30
[Arc] Add coroutine ops Arc Involving the `arc` dialect
#10522 opened May 21, 2026 by fabianschuiki Contributor Loading…
8
[FIRRTL] EliminateWires: preserve sv.attributes when converting WireOp to NodeOp
#10519 opened May 21, 2026 by bheneffe Loading…
14
[Synth] Add SAT-based exact synthesis pass
#10493 opened May 18, 2026 by uenoku Member Loading…
1
Bump slang 11.0
#10488 opened May 16, 2026 by mi-and-core • Draft
1
[ImportVerilog] Preserve declaration order across regular and interface-modport ports
#10468 opened May 14, 2026 by micprog Contributor Loading…
18
[HW] Add forceable wire support with HW RefType
#10447 opened May 12, 2026 by prithayan Contributor • Draft
[DRAFT][FIRRTLToHW] Emit sim.proc.print instead of sim.print
#10441 opened May 12, 2026 by nanjo712 Contributor • Draft
Add results to sv.ifdef
#10436 opened May 12, 2026 by prithayan Contributor • Draft
2
ProTip! Exclude everything labeled bug with -label:bug.