apb4

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PL-based UART IP core interfaced with the PS in Zynq 7000 SoC

fifo apb4

Design Verification Engineer portfolio: SystemVerilog, UVM, SVA, APB4, AXI4-Lite, coverage, RISC-V and FPGA.

fpga systemverilog uvm risc-v sva axi4 design-verification rtl-verification apb4 verification-engineer

Public portfolio of APB4 and AXI4 verification methodology using SystemVerilog, UVM, SVA and coverage.

coverage systemverilog uvm constrained-random sva axi4 design-verification rtl-verification apb4

Runnable APB4 master/slave RTL verification lab with UVM regressions, scoreboards, coverage, SVA and QuestaSim scripts.

coverage regression systemverilog questasim uvm amba sva design-verification rtl-verification apb4

Reusable SystemVerilog Assertions and self-checking simulation examples for APB4 protocol verification.

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